The present invention relates generally to a master slice system semiconductor integrated circuit device and the structure of a basic cell constituting the same.
Master slice systems are well known for standardizing a process from the design of an LSI to impurity diffusion, and only the subsequent circuit interconnection is carried out type by type in order to promptly meet various demands. This master slice system has advantages in that it yields small quantities of multiple types of products, shortens the development period and reduces the development costs.
A master slice type semiconductor integrated circuit (IC) device is produced by connecting a plurality of basic cells arranged in a matrix form or in one direction in accordance with the specifications of a completed article.
FIG. 16 shows the structure of an ordinary basic cell 100 mounted on a master slice type semiconductor IC device as described in, for example, Japanese Unexamined Patent Publication No. Hei 5-63046. This basic cell 100 comprises gate electrodes 101 and 102 of P type MOS transistors, a P type impurity diffusion region 103 equivalent to the drain terminal or source terminal of a P type MOS transistor, gate electrodes 104 and 105 of N type MOS transistors, an N type impurity diffusion region 106 equivalent to the drain terminal or source terminal of an N type MOS transistor, and two power supply lines 107 and 108.
FIG. 17 is a circuit diagram showing a delayed flip-flop circuit (hereinafter called "DFF circuit") 109 which is used as, for example, one memory element of a register.
In the figure, a DFF circuit 109 includes two stages of latch circuits 113 and 117 and a clock circuit 120. The latch circuit 113 has an inverter 110, a NAND gate 111 and a transfer gate 112. The latch circuit 117 has an inverter 114, a NAND gate 115 and a transfer gate 116. A signal Q and its inverted signal QN are output from the latch circuit 117 at the last stage. Transfer gates 118 and 119 connect or disconnect between an input terminal D and the latch circuit 113 and between the latch circuit 113 and the latch circuit 117, respectively. The individual transfer gates 112, 116, 118 and 119 are opened or closed by clock signals CK2 and CKN from a clock circuit 120. The clock circuit 120 is constructed by connecting two stages of inverters 121 and 122, and the clock circuit 120 outputs the clock signal CK2 and its inverted signal CKN.
The conventional basic cell 100 shown in FIG. 16 is suitable for producing a circuit with fewer elements, such as an inverter or a 2-input NAND or NOR gate. However, various problems arise in designing cells with a large chip-occupying area and multiple elements, such as a cell with plural types of circuits including latch circuits, transfer gates and inverters, as in the DFF circuit 109 shown in FIG. 17, a composite gate cell or a high drive-performance cell.
For example, the transfer gates 112, 116, 118 and 119 and the clock circuit 120, which need only a relatively small drive performance, and the output circuit (the inverter 114 and the NAND gate 115), which requires a large drive performance, are included in the DFF circuit 109 shown in FIG. 17. With the structure of the conventional basic cell 100, all the transistors are the same in size. Therefore, many transistors should be connected in parallel in constructing the output circuit if the transistors in the basic cell 100 are set to sizes that can cope with a transfer gate or a clock circuit. This increases the cell area, resulting in an increased chip area.
If the transistors in the basic cell 100 are set to sizes that can cope with the output circuit, large-size transistors should be used for a transfer gate or a clock circuit, both of which inherently require small-size transistors. This, again, inevitably increases the cell area.
FIG. 18 shows an example in which the DFF circuit 109 shown in FIG. 17 is designed by arranging eight basic cells 100 horizontally and connecting their associated terminals.
If large-size transistors are used for a transfer gate or a clock circuit, both of which should inherently be designed with small-size transistors, the input capacity is increased, which requires an external circuit having a high drive performance. This increases power consumption.
Since the conventional structure is made by combining multiple basic cells with simple structures, there is an increased chance of connecting circuits over transistors. This inevitably reduces the contact regions between the transistors and the circuit interconnection and increases contact resistances with the drains and sources. As a result, the drive performances of the individual transistors are reduced and it becomes necessary to add transistors to compensate for the lowered performance. This results in complicated circuit interconnections and an increased cell area.